In hardware implementation of a big integer modular multiplication algorithm of conventional technology, Montgomery modular multiplication algorithm is regarded as the most effective algorithm, which is an algorithm most suitable for hardware implementation as well.
At present, designing for implementing a modular multiplier of a big integer modular multiplication mostly employs Montgomery algorithm and its variants. The present design of the modular multiplier is for storing an intermediate result which is read when required in a next cycle; it is required to read and write a storage device frequently. However, performing reading and writing on the storage device requires taking clock periods so that the working efficiency of the modular multiplier is affected and data processing rate based on Montgomery modular multiplication is reduced; for example, the present Montgomery algorithm has a defect that the operation speed is slow for hardware implementation, which results in low efficiency and low speed of encryption algorithm such as RSA and ECC, etc.